This application is based upon and claims the benefit of priority from the prior art Japanese Patent Application No. 2001-340198 filed on Nov. 6, 2001, the entire contents of which are incorporated by reference.
The present invention relates to a semiconductor memory and a method of producing the same. Particularly, this invention relates to a cylinder-type stacked capacitor electrode for semiconductor memories and a method of producing such a type of stacked capacitor electrode.
One type of semiconductor memory is DRAM on/from which data can be written/retrieved. DRAM memory cells each consisting of one switching transistor and one capacitor have been widely used for semiconductor-memory integration owing to the simple structure.
One type of capacitor for such memory cells is a three-dimensionally structured capacitor that has been developed and used for maintaining capacitance at a certain degree or more in a reduced area on highly integrated DRAM.
The three-dimensionally structured capacitor is classified into a stacked type and a trench type. Especially, the stacked type is a good choice for highly integrated DRAM because of its stable performance with a relatively small capacitance and withstandingness against alpha ray and noises from circuitry.
Described with reference to FIGS. 56 to 58 is a known memory cell having such a stacked-type capacitor (called a stacked capacitor hereinafter) with a cylinder-type lower electrode, that has been under study and improvements. FIGS. 56 to 58 illustrate the known memory-cell structure: FIG. 56 is a plan view; FIG. 57 is a sectional view taken on line A-Axe2x80x2 of FIG. 56; and FIG. 58 is a sectional view taken on line B-Bxe2x80x2 of FIG. 56.
Provided on a semiconductor substrate 501 in FIGS. 56 to 58 are device-isolation regions 502 selectively formed thereon and MOS transistors (called just transistors herein after) Tr1, Tr2, . . . , each having source/drain diffusion layers 504a and 504b apart from each other and a gate electrode 507 coated with a silicon nitride film 506 provided via a gate insulating film 505 between the diffusion layers 504a and 504b, arranged, for example, in a matrix on a device-forming region 503 surrounded by the isolation regions 502.
The gate electrodes 507 lie in a row direction (transversal direction in FIG. 56) each shared by the transistors adjacent to each other in the row direction, functioning as word lines W0, W1, . . . .
Also formed over the semiconductor substrate 501 is a first interlayer insulating film (silicon oxide film) 520 having a buried capacitor plug 510 and a buried bit-line plug 511, both made of polycrystal silicon, on the diffusion layers 504a and 504b, respectively.
Formed on each first interlayer insulating film 520 having the capacitor plug 510 and the bit-line plug 511 is a second interlayer insulating film (silicon oxide film) 530 having a buried bit-line contact plug 512 made of, for example, tungsten coupled to the bit-line plug 511.
Formed between the adjacent transistors are bit lines BL0, BL1, . . . , made of, for example, tungsten in a column direction (longitudinal direction in FIG. 56), each bit line being electrically connected to the bit-line plug 511 via the bit-line contact plug 512. Further formed on each second interlayer insulating film 530 is a third interlayer insulating film (silicon oxide film) 540 having the bit lines BL0, BL1, . . . , buried therein.
Formed between the two adjacent bit lines is a capacitor contact plug 513 reaching the capacitor plug 510 through the third and second interlayer insulating films 540 and 530. The capacitor contact plug 513 and the capacitor plug 510 constitute a capacitor conductive plug 515.
Formed on each third interlayer insulating film 540 having the capacitor contact plug 513 is an insulator mount 550 made of, for example, a silicon nitride film, as a capacitor mount.
Provided in each insulator mount 550 is a through hole 551 reaching the capacitor conductive plug 515. Also formed is a cylinder-type lower electrode 561 having a rectangular bottom buried in each through hole 551 and penetrating into each insulator mount 550, electrically connected to the diffusion layer 504a via the capacitor conductive plug 515.
Each lower electrode 561 has dielectric films 562 formed on the inside and outside walls thereof. Formed on each lower electrode 561 via the dielectric film 562 is an upper electrode 563. The lower electrode 561, the dielectric film 562 and the upper electrode 563 constitute a capacitor 560.
Each capacitor 560 has insulating films 570 formed on the inside and outside wall thereof. Although not shown, another upper electrode and wirings are provided on each capacitor 560 to constitute a memory cell having the transistor and the cylinder-type capacitor.
Described next with reference to FIGS. 59A to 66B is a method of producing the known memory cell. FIGS. 59A to 66B illustrate a sectional view for each production step, taken on line A-Axe2x80x2, line B-Bxe2x80x2 or C-Cxe2x80x2 of FIG. 56.
As shown in FIG. 59A, the device-isolation regions 502 are selectively formed on the p-type semiconductor substrate 501, followed by formation of the gate electrodes 507 on the device-forming region 503 surrounded by the device-isolation regions 502, via the gate insulating films 505. Each gate electrode is coated with the silicon nitride film 506 and has a laminated structure of a polycrystal silicon layer and a tungsten layer. The semiconductor substrate 501 is then doped with n-type impurities using the gate electrodes 507 as a mask, thus the n-type source/drain diffusion layers 504a and 504b being formed for the MOS transistors (FIG. 59A).
A silicon oxide film is then deposited over the semiconductor substrate 501 having the gate electrodes 507 by plasma CVD (Chemical Vapor Deposition). The deposition is followed by CMP (Chemical Mechanical Polishing) for polishing the silicon oxide film until the silicon nitride film 506 on the gate electrodes 507 is exposed, having the first interlayer insulating film 520 buried between the two adjacent gate electrodes 507, as shown in FIG. 59B.
The first interlayer insulating film 520 formed on the diffusion layers 504a and 504b is selectively removed to provide openings 520a and 520b, respectively. Especially, the openings 520b are provided as having the width reaching over the device-isolation region 502 from the diffusion layer 504b. A phosphor-doped polycrystal silicon film is deposited over the semiconductor substrate 501 by LP (Low-Pressure)-CVD, followed by CMP, having the capacitor plugs 510 and the bit-line plugs 511, both made of a low-resistance polycrystal silicon film, buried in the openings 520a and 520b, respectively, on the diffusion layers 504a and 504b, respectively (FIGS. 59C and 59D).
The second interlayer insulating film 530 made of, for example, silicon oxide is formed on the first interlayer insulating film 520 having the buried capacitor plugs 510 and the buried bit-line plugs 511. The second interlayer insulating film 530 is then provided with openings 530a through each of which the bit-line plug 511 is exposed. A barrier metal film 531 is formed on the inside wall of each opening 530a. 
A conductive film made of, for example, tungsten is deposited on the second interlayer insulating film 530, thus the opening 530a being filled with the conductive film. The bit-line contact 512 made of tungsten is then buried into the opening 530a after having the conductive film polished by CMP (FIGS. 60A and 60B).
Another tungsten film is deposited and patterned using a specific-patterned silicon nitride film 541 provided on the tungsten film as a mask, thus forming the bit lines BL each connected to the bit-line plug 511 via the bit plug 512 (FIGS. 60C and 60D).
The third interlayer insulating film 540 made of, for example, an silicon oxide film is deposited on the second interlayer insulating film 523 having the bit liens BL, the third interlayer film 540 being then buried between the bit lines BL adjacent to each other after CMP-polish (FIGS. 61A and 61B).
Through holes 540a are provided each between two bit lines BL, as penetrating the third and second interlayer films 540 and 530 and reaching the capacitor plugs 510. A barrier metal film 532 is formed on the inside wall of each through hole 540a (FIGS. 62A and 62B).
A conductive film made of, for example, tungsten is deposited on the third interlayer insulating film 540, thus the through holes 540a being filled with the conductive film. The capacitor contact plug 513 made of tungsten is then buried into each through hole 540a after having the conductive film polished by CMP, thus the capacitor contact plug 513 and the capacitor plug 510 constituting the capacitor conductive plug 515 electrically connected to each diffusion layer 504a (FIGS. 63A and 63B).
Deposited nest successively by LP-CVD are the insulator mount 550 made of, for example, a silicon nitride film to support capacitor lower electrodes and a dummy insulating film 580 such as an silicon oxide film (FIG. 64A). The dummy insulating film 580 and the insulator mount 550 are patterned by known lithography and etching techniques to provide the through holes 551 so that the capacitor contact plugs 513 can be exposed therethrough (FIG. 64A).
A conductive film, such as, a ruthenium (Ru) film is then formed by LP-CVD on the inner wall and the bottom of the through holes 551 and also the dummy insulating film 580, followed by application of a photoresist film 590 so that the through holes 551 can be completely filled with the photoresist film (FIG. 64B).
The photoresist film 590 is polished by CMP, thus the through holes 551 being filled with the photoresist film 590, until the lower electrode 561 portions formed on the dummy insulating film 580 are removed (FIG. 65A).
The photoresist 590 filled in each of the through hole 551 is removed with thinner and then dummy insulating film 580 used for providing the through holes 551 is removed with a hydrofluoric-acid aqueous solution, thus forming the rectangular-cylinder type lower electrodes 561 on the capacitor conductive plugs 515, the bottom of each lower electrode being supported by the insulator mount 550 (FIG. 65B).
The dielectric film 562, such as, a TaO film is formed on the inside and outside walls of each lower electrode 561, and a conductive film, such as, a Ru film is formed by LP-CVD on the dielectric film 562. The conductive film is patterned to become the upper electrode 563. The lower electrode 561, the dielectric film 562 and the upper electrode 563 constitute each capacitor 560 (FIG. 66A).
The insulating film 570 is then deposited inside and outside the capacitors 560 and polished (FIG. 66B).
After that, wirings connected to the upper electrode are provided by known wiring techniques on each capacitor 560 to constitute a memory cell having one transistor and one cylinder-type capacitor.
The known memory cell described above, however, has the following disadvantages:
Each cylinder-type lower electrode 561 is supported by the insulator mount 550 such that the bottom of the electrode is surrounded by the mount. The bottom outer surface surrounded by the insulator mount 550 has no dielectric film 562 and the upper electrode 563 thereon, so that this bottom portion of the lower electrode will not work as a capacitor in operation.
With increased demand for further miniaturization and high integration in DRAM memories, it is a current trend that the area on which such a type of capacitor is to be formed is further reduced. And, one requirement for DRAM memory cells is capacitance consistency against alpha-ray induced soft errors or for enhanced signal strength in data retrieval. These trend and requirement cause such a capacitor to be higher and higher in height.
A thin insulator mount 550 for gaining high capacitance for such a capacitor could cause low mechanical strength for each lower electrode 561 to stand by itself, resulting in that the lower electrode 561 could fall down during stacked-capacitor assembly. On the contrary, a thick insulator mount 550 for protecting the lower electrode 561 from falling down could not provide a required capacitance.
Further disadvantages of the known memory cell are that each lower electrode 561 is thin, for example, 30 nm in thickness and hence mechanically weak, and it is supported by the insulator mount 550 only at its bottom. This structure could cause that the lower electrode 561 falls down during processes, such as, selective etching to the dummy insulating film between lower electrodes, removal of photoresist from the lower electrodes, formation of dielectric films and upper electrodes on the lower electrodes, and filling insulating materials in inside and outside capacitors, thus lowering manufacturing yields.
A semiconductor memory according to a first aspect of the present invention includes: at least one insulator mount formed over a semiconductor substrate; a plurality of cylinder-type stacked capacitors, a bottom of each capacitor being supported by the insulator mount, each capacitor having a lower electrode and an upper electrode facing each other via a dielectric film; and at least one beam-like insulator supporting a side portion of the lower electrode of each capacitor, the side portion being located between an upper edge of the lower electrode and the insulator mount.
Moreover, a semiconductor memory according to a second aspect of the present invention includes: at least one transistor formed in a surface of a semiconductor substrate; an insulating film formed over the transistor; a plurality of cylinder-type stacked capacitors, each capacitor having a cylinder-type lower electrode electrically connected to a diffusion layer of the transistor through the insulating film, a dielectric film covering inside and outside surfaces of the lower electrode and an upper electrode formed on the dielectric film; and at least one beam-like insulator supporting a side portion of the lower electrode of each capacitor, the side portion being apart from a lower edge of the lower electrode.
Furthermore, a method of producing a semiconductor memory according to a third aspect of the present invention includes: forming an inter-layer insulating film over a semiconductor substrate, the inter-layer insulating film having at least one conductive plug embedded therein, the conductive plug being electrically connected to a diffusion layer formed in the surface of the semiconductor substrate; forming a first insulating film on the inter-layer insulating film; forming a first dummy insulating film on the first insulating film; forming a beam-like insulator on the first dummy insulating film; selectively removing the first dummy insulating film and the first insulating film to provide a hole, an outer wall portion of the hole touching the beam-like insulator and a bottom of the hole reaching the conductive plug; forming a first conductive film extending from an inner wall of the hole to the bottom thereof, the first conductive film functioning as a lower electrode; selectively removing the first dummy insulating film in relation to the beam-like insulator and the first insulating film to have the lower electrode, the beam-like insulator and the first insulating film remaining un-removed; forming a dielectric film to cover inner and outer surfaces of the lower electrode; and forming a second conductive film on the dielectric film, the second conductive film functioning as an upper electrode.